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- Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
- IEEE Trans. VLSI Syst.
- 1998

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical… (More)

- Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
- DATE
- 2001

LPSAT is an LP-based comprehensive infrastructure designed to solve the satisfiability (SAT) problem for complex RTL designs containing both word-level arithmetic operators and bit-level Boolean logic. The presented technique uses a mixed integer linear program to model the constraints corresponding to both domains of the design. Our technique renders the… (More)

- Seiyang Yang, Maciej J. Ciesielski
- IEEE Trans. on CAD of Integrated Circuits and…
- 1991

- Maciej J. Ciesielski, Priyank Kalla, Serkan Askar
- IEEE Trans. Computers
- 2006

This work has been supported by a grant from the National Science Foundation, CCR-0204146, and in part by the international NSF/CNRS/DAAD supplement grant, INT-0233206. Abstract— Taylor Expansion Diagram (TED) is a compact, wordlevel, canonical representation for data flow computations that can be expressed as multi-variate polynomials. TEDs are based on a… (More)

- Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
- ICCD
- 1999

There are two major approaches to the synthesis of logic circuits. One is based on a predominantly algebraic factorization leading to AND/OR logic optimization. The other is based on classical Reed-Muller decompositionmethod and its related decision diagrams, which have been shown to be efficient for XOR-intensive arithmetic functions. Both approaches share… (More)

This paper presents a new, compact, canonicalgraph-based representation, called Taylor Expansion Diagrams(TEDs). It is based on a general non-binary decompositionprinciple using Taylor series expansion. It can be exploitedto facilitate the verification of high-level (RTL) designdescriptions. We present the theory behind TEDs, commentupon its canonicity… (More)

- Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
- HLDVT
- 2001

- Donald A. Joy, Maciej J. Ciesielski
- IEEE Trans. on CAD of Integrated Circuits and…
- 1993

- Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi
- 2015 52nd ACM/EDAC/IEEE Design Automation…
- 2015

The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification,… (More)