• Publications
  • Influence
A dynamic instruction set computer
A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructionsExpand
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Actor-Oriented Design of Embedded Hardware and Software Systems
In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is an abstraction layer in the design flow. For example, a core-basedExpand
  • 254
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Accelerator validation of an FPGA SEU simulator
An accelerator test was used to validate the performance of an FPGA single event upset (SEU) simulator. The Crocker Nuclear Laboratory cyclotron proton accelerator was used to irradiate the SLAAC1-V,Expand
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Constant Coefficient Multiplication Using Look-Up Tables
Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-basedExpand
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The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets
FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-Earth orbit, FPGAs (field programmable gate arrays) are susceptible to Single-Event Upsets (SEUs). In anExpand
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Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation
This study examines the single-event response of the Xilinx 28 nm Kintex-7 FPGA irradiated with heavy ions. Results for single-event effects on configuration SRAM cells, user-accessible Flip-FlopExpand
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Implementation Approaches for Reconfigurable Logic Applications
Reconfigurable FPGAs provide designers with new implementation approaches for designing high-performance applications. This paper discusses two basic implementation approaches with FPGAs: compiletimeExpand
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Evaluating TMR Techniques in the Presence of Single Event Upsets
Field programmable gate arrays (FPGAs) are sensitive to radiation-induced single event upsets (SEUs) within the configuration memory. Triple modular redundancy (TMR) is a technique commonly used toExpand
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High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond
  • M. Wirthlin
  • Computer Science, Engineering
  • Proceedings of the IEEE
  • 15 April 2015
Field-programmable gate arrays (FPGAs) have been shown to provide high computational density and efficiency for many computing applications by allowing circuits to be customized to any application ofExpand
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Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employExpand
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