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Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
TLDR
We present a procedure that translates the original formula into one in propositional logic by interpreting the formula over a domain of fixedlength bit vectors and using vectors of propositional variables to encode domain variables. Expand
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Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW
TLDR
We compare SAT-checkers and decision diagrams on the evalua-tion of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW micro-processors. Expand
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Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors
  • M. Velev, R. Bryant
  • Computer Science
  • Proceedings of the 38th Design Automation…
  • 18 June 2001
TLDR
We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. Expand
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Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors
TLDR
We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulae produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. Expand
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Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
TLDR
The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. Expand
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Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction
  • M. Velev, R. Bryant
  • Computer Science
  • Proceedings 37th Design Automation Conference
  • 1 June 2000
TLDR
We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. Expand
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Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
TLDR
We present a collection of ideas that allows the pipeline verification method pioneered by Burch and Dill [5] to scale very efficiently to dual-issue superscalar processors. Expand
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Boolean satisfiability with transitivity constraints
TLDR
We consider a variant of the Boolean satisfiability problem where a subset ϵ of the propositional variables appearing in formula <i>F</i><inf>sat</inf> encode a symmetric, transitive, binary relation over < i>N</i> elements. Expand
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Efficient and Accurate Value Prediction Using Dynamic Classification
TLDR
In an effort to increase instruction level parallelism in superscalar microprocessors, several recent works have proposed value prediction mechanisms to break the data dependency links between value-producing and value-consuming instructions. Expand
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Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
  • M. Velev
  • Computer Science
  • International Test Conference, . Proceedings. ITC…
  • 30 September 2003
TLDR
The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. Expand
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