We present a procedure that translates the original formula into one in propositional logic by interpreting the formula over a domain of fixedlength bit vectors and using vectors of propositional variables to encode domain variables.Expand

We compare SAT-checkers and decision diagrams on the evalua-tion of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW micro-processors.Expand

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors.Expand

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulae produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors.Expand

The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic.Expand

We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency.Expand

We present a collection of ideas that allows the pipeline verification method pioneered by Burch and Dill [5] to scale very efficiently to dual-issue superscalar processors.Expand

We consider a variant of the Boolean satisfiability problem where a subset Ďµ of the propositional variables appearing in formula <i>F</i><inf>sat</inf> encode a symmetric, transitive, binary relation over < i>N</i> elements.Expand

In an effort to increase instruction level parallelism in superscalar microprocessors, several recent works have proposed value prediction mechanisms to break the data dependency links between value-producing and value-consuming instructions.Expand

International Test Conference, . Proceedings. ITCâ€¦

30 September 2003

TLDR

The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations.Expand