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Algorithms for scalable synchronization on shared-memory multiprocessors
The principal conclusion is that contention due to synchronization need not be a problemin large-scale shared-memory multiprocessors, and the existence of scalable algorithms greatly weakens the case for costly special-purpose hardware support for synchronization, and provides protection against so-called “dance hall” architectures.
Simple, fast, and practical non-blocking and blocking concurrent queue algorithms
Experiments on a 12-node SGI Challenge multiprocessor indicate that the new non-blocking queue consistently outperforms the best known alternatives; it is the clear algorithm of choice for machines that provide a universal atomic primitive (e.g., compare_and_swap or load_linked/store_conditional).
NOrec: streamlining STM by abolishing ownership records
An ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusually clean semantics is presented, and the experience suggests that NOrec may be an ideal candidate for such a software system.
Advanced contention management for dynamic software transactional memory
This work considers both visible and invisible versions of read access, and benchmarks that vary in complexity, level of contention, tendency toward circular dependence, and mix of reads and writes, and identifies a candidate default policy.
Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model
The notion of durable linearizability is introduced to govern the safety of concurrent objects under this failure model and a corresponding relaxed, buffered variant which ensures that the persistent state in the event of a crash is consistent but not necessarily up to date.
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
- G. Semeraro, G. Magklis, Rajeev Balasubramonian, D. Albonesi, S. Dwarkadas, M. Scott
- Computer ScienceProceedings Eighth International Symposium on…
- 2 February 2002
An alternative approach is described, which is called a multiple clock domain (MCD) processor, in which the chip is divided into several clock domains, within which independent voltage and frequency scaling can be performed.
Lowering the Overhead of Nonblocking Software Transactional Memory
This work considers the design of low-overhead, obstruction-free software transactional memory for non-garbage-collected languages and eliminates dynamic allocation of transactional metadata and co-locates data that are separate in other systems, thereby reducing the expected number of cache misses on the common-case code path.
Nonblocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors
The results indicate that the nonblocking queue consistently outperforms the best known alternatives and that data-structure-specific nonblocking algorithms, which exist for queues, stacks, and counters, can work extremely well.
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
A family of hybrid TMs built using the recent NOrec STM algorithm is introduced that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions.
Scalable reader-writer synchronization for shared-memory multiprocessors
Reader-writer locks that similarly exploit locality to achieve scalability are presented, with variants for reader preference, writer preference, and reader-writer fairness.