M. Schindewolf

Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Expand

This paper describes the design of a transactional memory extension for GCC, and highlights research challenges and perspectives enabled by this design. Expand

The rising integration level enables combining more logic on a single chip. Expand

The goal of this work is to establish a POSIX-like thread model in a distributed system, to enable a smooth upgrade path for legacy software. Expand

We use the Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s to accelerate an application for searching homologous sequences. Expand

This paper presents a methodology and an implementation to capture event logs representing the behavior of a transactional memory application and study the impact of the trace generation on the throughput of the STM system. Expand

This paper evaluates TM implementations of two algorithmic variations of the wide-spread conjugate gradients method (CG) regarding their performance on multi-core CPUs employing TM. Expand

In this paper, we introduce our framework and demonstrate its applicability to benchmarks as well as real world numerical workloads. Expand

This paper shows the runtime and cache-efficiency of parallel implementations of the Conjugate Gradients Method based on the three paradigms Software Transactional Memory (STM), OpenMP and Pthreads. Expand

Transactional Memory (TM) has been proposed as an architectural extension to enable lock-free data structures. Expand