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RT-Level ITC'99 Benchmarks and First ATPG Results
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-levelExpand
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On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running onExpand
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Microprocessor Software-Based Self-Testing
This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- andExpand
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Soft-error detection using control flow assertions
Over the last few years, an increasing number of safety-critical tasks have been demanded of computer systems. In this paper, a software-based approach for developing safety-critical applications isExpand
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New static compaction techniques of test sequences for sequential circuits
This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences soExpand
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An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
In this paper we describe an FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits. Suitable techniques are proposed, allowing emulatingExpand
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Soft-error detection through software fault-tolerance techniques
The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a high-level language. The transformations aim at making theExpand
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GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits
This paper deals with automated test pattern generation for large synchronous sequential circuits and describes an approach based on genetic algorithms. A prototype system named GATTO is used toExpand
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Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from oneExpand
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Simulation-based analysis of SEU effects in SRAM-based FPGAs
SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA's configuration memory, may affect dramatically the functionsExpand
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