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Fast Heuristic Minimization of Exclusive-Sums-of-Products
Exclusive-Sums-Of-Products (ESOPs) play an important role in logic synthesis and design-for-test. This paper presents an improved version of the heuristic ESOP minimization procedure proposed inExpand
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis
This paper constitutes the first successful experience of applying formal methods and satisfiability to quantum logic synthesis, thus synthesizing in principle arbitrary multi-output Boolean functions with quantum gate library. Expand
Logic Synthesis of Reversible Wave Cascades
This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms implementing incompletely specified Boolean functions, and preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks. Expand
An algorithm for bi-decomposition of logic functions
Experimental results over MCNC benchmarks show that this approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time. Expand
Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits
We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for moreExpand
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams
An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented and a 25% improve ment in size over OBDDs is observed. Expand
Evolving quantum circuits using genetic algorithm
A generic GA to evolve arbitrary quantum by using genetic algorithm as well as a specific encoding that reduces the time of calculating the resultant unitary matrices of chromosomes is proposed. Expand
Quantum ternary parallel adder/subtractor with partially-look-ahead carry
This paper proposes quantum realization of a ternary full-adder using macro-level Ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternaries 1-qutrit and Muthukrishnan-Stroud gates and proposes realization ofA ternARY parallel adder with partially-look-ahead carry. Expand
Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions
  • N. Song, M. Perkowski
  • Mathematics, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1 April 1996
Evaluation on benchmark functions is given and it proves the superiority of the program to those known from the literature on the basis of power and efficiency. Expand
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
A very fast computer program that accepts a Boolean function as an array of multi-output disjoint cubes and returns a mixed-polarity Generalized Reed-Muller Form is presented. Such circuits oftenExpand