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Modified Montgomery modular multiplication and RSA exponentiation techniques
Modified Montgomery multiplication and associated RSA modular exponentiation algorithms and circuit architectures are presented. These modified multipliers use carry save adders (CSAs) to perform
Fast Montgomery modular multiplication and RSA cryptographic processor architectures
TLDR
New, generic silicon architectures for implementing Montgomery's multiplication algorithm are presented and it is shown that using a four-to-two CSA with two extra registers rather than a five- to- two CSA leads to a useful reduction in the critical path of the multiplier, albeit at the expense of a small increase in circuitry.
High-performance FPGA implementation of DES using a novel method for implementing the key schedule
TLDR
A generic, parameterisable key scheduling core is presented, which can be utilised in pipelinable private-key encryption algorithms and the broader applicability of the method to other encryption algorithms is illustrated.
A single-chip IPSEC cryptographic processor
TLDR
A novel single-chip hardware IPSec cryptographic design is described, which comprises the Rijndael encryption algorithm and HMAC-SHA-1 authentication algorithm, and is capable of supporting any application requiring authentication and/or encryption.
An FPGA elliptic curve cryptographic accelerator over GF(p)
A new FPGA architecture for performing the arithmetic functions needed in elliptic curve cryptographic primitives over GF(p) is presented. The embedded 18×18-bit multipliers and fast carry look-ahead
Improved Montgomery modular inverse algorithm
A new, single and unified Montgomery modular inverse algorithm, which performs both classical and Montgomery modular inversion, is proposed. This reduces the number of Montgomery multiplication
A high performance FPGA implementation of DES
  • M. McLoone, J. McCanny
  • Computer Science
    IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS…
  • 11 October 2000
TLDR
This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encryption algorithm, which runs at an encryption rate of 3.87 Gbits/s using Xilinx Virtex FPGA technology making this the fastest single-chip DES FPGAs implementation reported to date.
Randomly Shifted Certification Authority Authentication Protocol for MANETs
TLDR
RASCAAL is the first authentication protocol which proposes the concept of dynamically formed short lived random clusters with no prior knowledge of the cluster head and implements the idea of a random ACTIVE CA selection and CA role shift in the network.
Existing Wireless Network Security Mechanisms and their Limitations for Ad Hoc Networks
TLDR
The fundamental limitations of these underlying techniques and protocols are described and why they cannot be directly employed in mobile ad hoc networks (MANETs) are discussed.
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