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Wattch: a framework for architectural-level power analysis and optimizations
TLDR
This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Expand
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Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
TLDR
This paper examines the research decisions and design tradeoffs that arise when applying wireless peer-to-peer networking techniques in a mobile sensor network designed to support wildlife tracking for biology research. Expand
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Cache decay: exploiting generational behavior to reduce cache leakage power
TLDR
This paper examines methods for reducing leakage power within the cache memories of the CPU. Expand
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Dynamic thermal management for high-performance microprocessors
  • D. Brooks, M. Martonosi
  • Computer Science
  • Proceedings HPCA Seventh International Symposium…
  • 20 January 2001
TLDR
In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. Expand
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Data compression algorithms for energy-constrained devices in delay tolerant networks
TLDR
We show how different amounts of compression can lead to energy savings on both the compressing node and throughout the network and that the savings depends heavily on the radio hardware. Expand
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An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
TLDR
A global multi-core power manager can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget. Expand
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SHiP: Signature-based Hit Predictor for high performance caching
TLDR
We propose a Signature-based Hit Predictor (SHiP) to learn the re-reference behavior of cache lines belonging to each signature. Expand
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Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing environment-readyExpand
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Runtime power monitoring in high-end processors: methodology and empirical data
  • C. Isci, M. Martonosi
  • Computer Science
  • Proceedings. 36th Annual IEEE/ACM International…
  • 3 December 2003
TLDR
We present live total power measurements for Intel Pentium 4 processors, and also provides power breakdowns for 22 of the major CPU subunits over minutes of SPEC2000. Expand
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Erasure-coding based routing for opportunistic networks
TLDR
We use simulation to compare the routing performance of using erasure codes in DTN with four other categories of forwarding algorithms proposed in the literature. Expand
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