• Publications
  • Influence
Wattch: a framework for architectural-level power analysis and optimizations
Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
The goal is to use the least energy, storage, and other resources necessary to maintain a reliable system with a very high `data homing' success rate and it is believed that the domain-centric protocols and energy tradeoffs presented here for ZebraNet will have general applicability in other wireless and sensor applications.
Cache decay: exploiting generational behavior to reduce cache leakage power
This paper examines methods for reducing leakage power within the cache memories of the CPU by invalidating and "turning off" cache lines when they hold data not likely to be reused, and proposes adaptive decay-based policies that make energy-minimizing policy choices on a per-application basis.
Dynamic thermal management for high-performance microprocessors
  • D. Brooks, M. Martonosi
  • Engineering, Computer Science
    Proceedings HPCA Seventh International Symposium…
  • 20 January 2001
This work investigates dynamic thermal management as a technique to control CPU power dissipation and explores the tradeoffs between several mechanisms for responding to periods of thermal trauma and the effects of hardware and software implementations.
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
The results show that the best architected policies can come within 1% of the performance of an ideal oracle, while meeting a given chip-level power budget, and are significantly better than static management, even if static scheduling is given oracular knowledge.
Data compression algorithms for energy-constrained devices in delay tolerant networks
This paper discusses the design issues involved with implementing, adapting, and customizing compression algorithms specifically geared for sensor nodes and shows how different amounts of compression can lead to energy savings on both the compressing node and throughout the network.
Runtime power monitoring in high-end processors: methodology and empirical data
  • C. Isci, M. Martonosi
  • Computer Science
    Proceedings. 36th Annual IEEE/ACM International…
  • 3 December 2003
This paper describes a technique for a coordinated measurement approach that combines real total power measurement with performance-counter-based, per-unit power estimation and also gives experiences and empirical application results that can provide a basis for future power-aware research.
SHiP: Signature-based Hit Predictor for high performance caching
This paper proposes a novel Signature-based Hit Predictor (SHiP) to learn the re-reference behavior of cache lines belonging to each signature, and finds that SHiP offers substantial improvements over the baseline LRU replacement and state-of-the-art replacement policy proposals.
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics
Graphicionado augments the vertex programming paradigm, allowing different graph analytics applications to be mapped to the same accelerator framework, while maintaining flexibility through a small set of reconfigurable blocks, for high-performance, energy-efficient processing of graph analytics workloads.
Hardware design experiences in ZebraNet
This paper discusses the techniques for devising efficient power supplies for sensor networks, methods of managing the energy consumption of the nodes, and methods of manage the peripheral devices including the radio, flash, and sensors, and concludes by evaluating the design of the ZebraNet nodes and discussing how it can be improved.