• Publications
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Analyzing on-chip communication in a MPSoC environment
TLDR
This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate the communication sub-system with functional traffic generated by real applications running on top of a configurable number of ARM processors. Expand
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Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking
TLDR
We propose an effective solution to the problem of the leakage-aware partitioning of a memory into disjoint subblocks; in particular, we target scratchpad memories, which are commonly used in some embedded systems as a replacement for caches. Expand
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Cache coherence tradeoffs in shared-memory MPSoCs
TLDR
A comparative energy and performance analysis of cache-coherence support schemes in multiprocessor systems on chips . Expand
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Partitioned cache architectures for reduced NBTI-induced aging
TLDR
We propose an architectural solutions that is based on the idea of partitioning a memory into multiple banks of identical size. Expand
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SystemC co-simulation for core-based embedded systems
TLDR
We present a framework that allows to co-simulate the hardware under development and the software, in a system extending context as well as in a CPU-centered design. Expand
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A portable 3D Imaging FMCW MIMO Radar Demonstrator with a 24x24 Antenna Array for Medium Range Applications
Multiple-Input-Multiple-Output (MIMO) radars have been shown to improve target detection for surveillance applications thanks to their proven high performance properties. In this paper, the design,Expand
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Tag overflow buffering: an energy-efficient cache architecture
TLDR
We propose a novel energy-efficient memory architecture which relies on the use of a cache with a reduced number of tag bits which allows us to dynamically update the value of the reference locality contained in the buffer. Expand
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Architectural Leakage-Aware Management of Partitioned Scratchpad Memories
TLDR
We propose an explorative solution to the problem of leakage-aware partitioning of a memory into disjoint sub-blocks, with a marginal overhead in execution time, thanks to an effective implementation of low-leakage sleep state. Expand
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Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors
TLDR
This work provides an effort in that sense, showing energy/performance tradeoffs for different snoop-based protocols on a realistic MPSoC architecture. Expand
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A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a $24\times 24$ Antenna Array for Medium-Range Applications
TLDR
In this paper, the design, implementation, and results of a complete 3-D imaging frequency-modulated continuous-wave MIMO radar demonstrator are presented. Expand
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