• Publications
  • Influence
Variation tolerant NoC design by means of self-calibrating links
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC architectures usingExpand
  • 33
  • 4
  • PDF
Cosimulation-based power estimation for system-on-chip design
We present efficient power estimation techniques for hardware-software (HW-SW) system-on-chip (SoC) designs. Our techniques are based on concurrent and synchronized execution of multiple powerExpand
  • 43
  • 2
Hardware Scheduling Support in SMP Architectures
In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means ofExpand
  • 25
  • 2
  • PDF
Behavioral-level test vector generation for system-on-chip designs
Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when system-on-chip design is considered. In a top-down design flow, designers would greatly benefitExpand
  • 29
  • 2
  • PDF
On the evaluation of fairness for input queue switches
Packet switches are required to support quality of service (QoS), that is, the capability to differentiate packet servicing on a flow basis, ensuring switching objectives such as guaranteedExpand
  • 7
  • 2
A compilation-based software estimation scheme for hardware/software co-simulation
High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem ofExpand
  • 72
  • 1
  • PDF
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculated by a softwareExpand
  • 68
  • 1
  • PDF
Compilation-based software performance estimation for system level design
The paper addresses embedded software performance estimation. Known approaches use either behavioral simulation with timing annotations, or a clock cycle-accurate model of instruction executionExpand
  • 44
  • 1
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of aExpand
  • 24
  • 1
Evaluating system dependability in a co-design framework
The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at every step of the designExpand
  • 16
  • 1
  • PDF