• Publications
  • Influence
Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming techniqueExpand
  • 72
  • 4
Thick-Strained-Si/Relaxed-SiGe Structure of High-Performance RF Power LDMOSFETs for Cellular Handsets
A strained-Si/relaxed-SiGe structure was applied to laterally diffused MOSFETs (LDMOSFETs) in order to improve the PAE of cellular handset RF power-amplifier applications. The LDMOSFETs wereExpand
  • 10
  • 1
Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage
Strained-silicon MOSFETs with both high breakdown voltage and low leakage current needed for RF/analog applications were investigated. Proper control of junction-depth profile andExpand
  • 17
High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure
We applied a strained-Si/relaxed-SiGe structure to LDMOSFETs in order to improve the power-added efficiency (PAE) of cellular handset RF power amplifier applications. Our LDMOSFETs were fabricated inExpand
  • 8
Strained-silicon MOSFETs of low leakage current and high breakdown voltage for analog applications
Strained-silicon MOSFETs of both high breakdown voltage and low leakage current were fabricated by employing a thick strained-silicon layer. It is demonstrated that proper control of junction depthExpand
  • 9
Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation
We developed a new bulk strained Si/SiGe CMOS technology free from any Ge-related problems, which has a 90- to 110-nm strained Si layer thicker than the limit at which misfit dislocations occur and aExpand
  • 5