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- Publications
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Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
- K. Okano, T. Izumida, +19 authors H. Ishiuchi
- Materials Science
- IEEE InternationalElectron Devices Meeting…
- 5 December 2005
The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique… Expand
Thick-Strained-Si/Relaxed-SiGe Structure of High-Performance RF Power LDMOSFETs for Cellular Handsets
- M. Kondo, N. Sugii, +8 authors I. Yoshida
- Materials Science
- IEEE Transactions on Electron Devices
- 30 November 2006
A strained-Si/relaxed-SiGe structure was applied to laterally diffused MOSFETs (LDMOSFETs) in order to improve the PAE of cellular handset RF power-amplifier applications. The LDMOSFETs were… Expand
Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage
- M. Kondo, N. Sugii, +7 authors I. Yoshida
- Materials Science
- IEEE Transactions on Electron Devices
- 24 April 2006
Strained-silicon MOSFETs with both high breakdown voltage and low leakage current needed for RF/analog applications were investigated. Proper control of junction-depth profile and… Expand
High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure
- M. Kondo, N. Sugii, +8 authors I. Yoshida
- Materials Science
- IEEE InternationalElectron Devices Meeting…
- 5 December 2005
We applied a strained-Si/relaxed-SiGe structure to LDMOSFETs in order to improve the power-added efficiency (PAE) of cellular handset RF power amplifier applications. Our LDMOSFETs were fabricated in… Expand
Strained-silicon MOSFETs of low leakage current and high breakdown voltage for analog applications
- N. Sugii, M. Kondo, +7 authors I. Yoshida
- Materials Science
- Digest of Technical Papers. Symposium on VLSI…
- 14 June 2005
Strained-silicon MOSFETs of both high breakdown voltage and low leakage current were fabricated by employing a thick strained-silicon layer. It is demonstrated that proper control of junction depth… Expand
Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation
- M. Miyamoto, N. Sugii, +4 authors K.. Ohnishi
- Materials Science
- IEEE Transactions on Electron Devices
- 27 August 2007
We developed a new bulk strained Si/SiGe CMOS technology free from any Ge-related problems, which has a 90- to 110-nm strained Si layer thicker than the limit at which misfit dislocations occur and a… Expand