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KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers
TLDR
In this paper we propose a new family of very efficient hardware oriented block ciphers divided into two flavors. Expand
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PRINCE - A Low-latency Block Cipher for Pervasive Computing Applications (Full version)
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spongent: A Lightweight Hash Function
TLDR
This paper proposes spongent - a family of lightweight hash functions with hash sizes of 88 (for preimage resistance only), 128, 160, 224, and 256 bits based on a sponge construction instantiated with a present-type permutation, following the hermetic sponge strategy. Expand
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PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract
TLDR
This paper presents a block cipher that is optimized with respect to latency with a very competitive chip area compared to known solutions. Expand
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Fides: Lightweight Authenticated Cipher with Side-Channel Resistance for Constrained Hardware
TLDR
We present a novel lightweight authenticated cipher optimized for hardware implementations called Fides. Expand
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SPONGENT: The Design Space of Lightweight Cryptographic Hashing
TLDR
We explore the design space of lightweight hash functions based on the sponge construction instantiated with present-type permutations. Expand
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Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods
TLDR
This paper proposes two improved interleaved modular multiplication algorithms based on Barrett and Montgomery modular reduction. Expand
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Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates
TLDR
We propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Expand
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Prototyping platform for performance evaluation of SHA-3 candidates
TLDR
The objective of the SHA-3 NIST competition is to select, from multiple competing candidates, a standard algorithm for cryptographic hashing. Expand
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Low-Latency ECDSA Signature Verification—A Road Toward Safer Traffic
TLDR
An application-specified integrated circuit implementation of a dedicated ECDSA verification engine that can reach verification rates of up to 27 000 verifications per second, which is by far the fastest implementation on a single core reported in the literature. Expand
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