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Single event phenomena in atmospheric neutron environments
Describes direct experimental measurements of neutron-induced single event effect (SEE) rates in commercial high-density static random access memories in a neutron environment characteristic of thatExpand
Compact modeling and simulation of accelerated circuit aging
TLDR
A compact model is derived for accelerated aging by analyzing the underlying mechanism, which connects the degradation rate with both reliability physics and circuit topology and is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. Expand
A compact SPICE model for statistical post-breakdown gate current increase due to TDDB
We developed a compact SPICE model capable of modeling the increases in post-breakdown (BD) gate current (IG_BD) due to time-dependent dielectric breakdown (TDDB), for circuit level simulations.Expand
Built-in testable error detection and correction
A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1- mu m CMOS,Expand
A testable CMOS synchronous counter
A testable design of a CMOS synchronous counter is presented with test vectors that provide 100% coverage of stuck-at and stuck-open faults in a time of order L/sup 2/, where L is the bit length ofExpand
An age-aware library for reliability simulation of digital ICs
A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account keyExpand
Accelerated BTI degradation under stochastic TDDB effect
TLDR
Based on stochastic trapping/detrapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data, demonstrating a significant increase in failure rate due to accelerated BTI. Expand
A BIST design of structured arrays with fault-tolerant layout
  • M. Katoozi, M. Soma
  • Engineering, Computer Science
  • International Test Conference Proceeding@m_New…
  • 12 September 1988
TLDR
A BIST (built-in self-test)-compatible method for the design, layout, and test of structured logic arrays is presented, which eliminates the need for placing shift registers and exclusive-OR gates on the product lines of the array. Expand
Adaptive accelerated aging with 28nm HKMG technology
Device and circuit reliability analysis lacks a direct validation of the lifetime. Usually, aging in devices is extrapolated from a short-term measurement, resulting in unreliable prediction of theExpand
Low overhead built-in testable error detection and correction with excellent fault coverage
A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with thisExpand
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