M. Irwin

Publications552
h-index60
Citations14,088
Highly Influential Citations674
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Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from…
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Analysis of error recovery schemes for networks on chips
TLDR
This article explores error control mechanisms at the data link and network layers and presents the schemes' architectural details to investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
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The design and use of simplePower: a cycle-accurate energy estimation tool
TLDR
This paper uses the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization on the datapath, memory and on-chip bus energy, respectively.
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Dynamic management of scratch-pad memory space
TLDR
A compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework that uses both loop and data transformations is proposed that indicates significant reductions in data transfer activity between SPM and off-chip memory.
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Toward Increasing FPGA Lifetime
TLDR
This work analyzes the impact of two different types of hard errors, namely, Time- Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) on FPGAs, and studies the performance degradation of FPGA over time caused by Hot-Carrier Effects and Negative Bias Temperature Instability.
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Fault tolerant algorithms for network-on-chip interconnect
TLDR
This work examines fault tolerant communication algorithms for use in the NoC domain and finds that the redundant random walk algorithm offers significantly reduced overhead while maintaining useful levels of fault tolerance.
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SEAT-LA: a soft error analysis tool for combinational logic
TLDR
A new approach is proposed, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element.
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VLSI architectures for the discrete wavelet transform
TLDR
A class of VLSI architectures based on linear systolic arrays, for computing the 1-D Discrete Wavelet Transform (DWT), is presented and these architectures are shown to be optimal in both computation time and in area.
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Soft error and energy consumption interactions: a data cache perspective
TLDR
This work presents an adaptive error coding scheme that treats dirty and clean data cache blocks differently, and presents an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability.
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Three-dimensional cache design exploration using 3DCacti
TLDR
A delay and energy model, 3DCacti, is presented, to explore different 3D design options of partitioning a cache, and allows partitioning of the cache across different device layers at various levels of granularity.
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