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  • Influence
FinFET design considerations based on 3-D simulation and analytical modeling
Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonablyExpand
  • 252
  • 11
Modeling line edge roughness effects in sub 100 nanometer gate length devices
A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a givenExpand
  • 147
  • 11
  • Open Access
Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes requiredExpand
  • 137
  • 11
Extension and source/drain design for high-performance FinFET devices
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. AngledExpand
  • 217
  • 10
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
  • K. Rim, J. Chu, +16 authors H. P. Wong
  • Engineering
  • Symposium on VLSI Technology. Digest of Technical…
  • 11 June 2002
Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltageExpand
  • 147
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Silicon Device Scaling to the Sub-10-nm Regime
In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) belowExpand
  • 428
  • 7
  • Open Access
Extreme scaling with ultra-thin Si channel MOSFETs
We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOIExpand
  • 180
  • 7
Monte Carlo modeling of threshold variation due to dopant fluctuations
This paper presents a new, 3-D Monte Carlo approach for modeling random dopant fluctuation effects in MOSFETs. The method takes every silicon atom in the device into account and is generallyExpand
  • 147
  • 7
High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices
Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies.Expand
  • 119
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Strained Si NMOSFETs for high performance CMOS technology
Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time,Expand
  • 134
  • 7
  • Open Access