• Publications
  • Influence
Synergistic Processing in Cell's Multicore Architecture
TLDR
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. Expand
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A methodology for the real world
TLDR
Register allocation may be viewed as a graph coloring problem. Expand
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Register Allocation Via Coloring
TLDR
This paper describes the Register Allocation Phase of an experimental PL/I compiler for the IBM System/370. Expand
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Register allocation via graph coloring
TLDR
The basic idea behind register allocation via graph coloring is to reduce register spillage by globally assigning variables to registers across an entire program module via the five basic steps below: I. Assign each object (intermediate result name, variable, or constant) to a distinct symbolic register called si. Expand
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An overview of the PL.8 compiler
TLDR
The PL.8 compiler accepts multiple source languages and produces high quality object code for several different machines. Expand
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A Perspective on the 801/Reduced Instruction Set Computer
TLDR
This paper described the background and evolution of these ideas in the context of the 801 experimental minicomputer project, which questioned the trend toward complexity in computer architecture. Expand
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A case for the GOTO
TLDR
In recent years there has been much controversy over the use of the <underline>goto</underline>. Expand
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Exploiting Instruction Level Parallelism In Processors By Caching Scheduled Groups
  • R. Nair, M. Hopkins
  • Computer Science
  • Conference Proceedings. The 24th Annual…
  • 1 June 1997
TLDR
In this paper we propose a processor implementation which dynamically schedules groups of instructions while executing them on a fast simple engine and caches them for repeated execution on a VLIW-type engine. Expand
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A novel SIMD architecture for the cell heterogeneous chip-multiprocessor
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