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New Frame Rate Up-Conversion Algorithms With Low Computational Complexity
This paper proposes a new frame rate up-conversion (FRUC) algorithm to reduce the computational complexity and to improve the peak signal-to-noise ratio (PSNR) performance. The proposed FRUCExpand
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New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy
The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategyExpand
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Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder
This paper proposes an enhanced degree computationless modified Euclid's (E-DCME) algorithm for Reed-Solomon decoder. The critical path delay of the proposed E-DCME algorithm requires only TMul + TExpand
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New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder
This paper proposes a new degree computationless modified Euclid (DCME) algorithm and its dedicated architecture for Reed-Solomon (RS) decoder. This architecture has low hardware complexity comparedExpand
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A high-speed FFT processor for OFDM systems
This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses aExpand
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ASIP approach for implementation of H.264/AVC
This paper presents an application-specific instruction set processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra prediction, deblockingExpand
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A general purpose SliM-II image processor
The paper presents a new version of the sliding memory plane image processor (SliM-II) which integrates a linear array of sixty-four 8-bit processing elements (PEs) on a single chip. In contrast toExpand
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Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture
This paper proposes a new simplified degree computationless modified Euclid's algorithm (S-DCME) and its architecture for Reed-Solomon decoders. The proposed S-DCME algorithm uses the new initialExpand
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A Sliding Memory Plane Array Processor
A mesh-connected single-input multiple-data (SIMD) architecture called a sliding memory plane (SliM) array processor is proposed. Differing from existing mesh-connected SIMD architectures, SliM hasExpand
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Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoders
An enhanced degree computationless modified Euclid's (E-DCME) algorithm for Reed-Solomon (RS) decoders is proposed. The algorithm does not require the degree computation and comparison circuits. InExpand
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