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Estimate of signal probability in combinational logic networks
Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in theExpand
Multiview 3D reconstruction in geosciences
Comparison of the models obtained using the presented method with those obtained using a precise laser scanner shows that multiview 3D reconstruction yields models that present a root mean square error/average linear dimensions between 0.11 and 0.68%. Expand
Novel design for testability schemes for CMOS ICs
The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in theExpand
On-line detection of logic errors due to crosstalk, delay, and transient faults
A detector is proposed that allows the on-line detection of such logic errors, and that is self-checking with respect to a wide set of possible internal faults representative of realistic failures, including crosstalk, delay, and transient faults. Expand
An analytical model for the aliasing probability in signature analysis testing
The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a functionExpand
Testability measures in pseudorandom testing
The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused byExpand
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
New definitions are proposed here to consider the analog and dynamic effects of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits, and to ensure that they do not produce any problem at the system level. Expand
Bridging fault modeling and simulation for deep submicron CMOS ICs
A new fault model is proposed to account for bridging faults in deep submicron CMOS digital ICs in a way that is independent of electrical parameters and provides a significant coverage metric. Expand
Regression Models for Behavioral Power Estimation
This work proposes an accurate and general behavioral power modeling approach especially suited for synthesis-based design ows making use of a library of hard macros implementing behavioral operators based on the theory of linear regression. Expand
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) that exploits the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. Expand