• Publications
  • Influence
Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard
This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms ofExpand
  • 35
  • 9
  • PDF
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V
An increasing amount of embedded memory is used in today's ICs and consequently the design of low-power, high-density SRAM is becoming critical. With technology scaling, it is becoming increasinglyExpand
  • 49
  • 6
Technologies for Ultradynamic Voltage Scaling
Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applicationsExpand
  • 111
  • 5
  • PDF
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access
This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switchingExpand
  • 44
  • 3
Self-aware computing in the Angstrom processor
Addressing the challenges of extreme scale computing requires holistic design of new programming models and systems that support those models. This paper discusses the Angstrom processor, which isExpand
  • 79
  • 2
  • PDF
A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier
8T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture andExpand
  • 22
  • 2
  • PDF
A Reconfigurable 8 T Ultra-Dynamic Voltage Scalable ( U-DVS ) SRAM in 65 nm CMOS
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamicExpand
  • 20
  • 2
  • PDF
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics
This paper introduces a framework for designing data-dependent SRAMs taking advantage of statistical dependencies present in the binary values processed and stored in the intermediary stages ofExpand
  • 5
  • 2
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder
The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devicesExpand
  • 49
  • 1
  • PDF
A 28 nm 0.6 V Low Power DSP for Mobile Applications
Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However,Expand
  • 64
  • 1
  • PDF