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Functional verification of large ASICs
TLDR
This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASPCs designed at Nortel. Expand
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Integrating Behavior and Timing in Executable Specifications
TLDR
We present a modeling methodology and tool set for the rapid development of executable HDL models. Expand
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A stimulus/response system based on hierarchical timing diagrams
TLDR
The authors present a tool that captures timing specifications from hierarchical timing diagrams and models them using hierarchical constraint graphs. Expand
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Accelerating concurrent hardware design with behavioural modelling and system simulation
TLDR
This paper describes a functional hardware verification methodology for ASIC intensive products. Expand
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Universal matrices for the N-dimensional finite element
New universal matrices are presented for the n-dimensional simplex element. Their use recasts complex integrals into sums and products of universal matrices with coordinate-independent geometricExpand
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De l'Alpha à l'Oméga
Apocalypse 1:8 : « Je suis l'alpha et l'oméga, le principe et la fin, dit le Seigneur Dieu, celui qui est, qui était, et qui vient, le Tout-Puissant. ». Nous savons tous que Jésus-Christ est l'alphaExpand
Les cinq doigts de la « MAIN »
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Database structure for plasma modeling programs
Summary form only given. The data structure requirements of plasma programs are stated by defining suitable abstract data types. These abstractions are then reduced to data structures and a group ofExpand
Étude éthologique de la dominance sociale lors de la formation de groupes restreints d'enfants d'âge préscolaire
Cette etude s'interesse principalement a l'etablissement des rapports de dominance lors de la formation de groupes restreints chez les enfants d'âge prescolaire. Notre echantillon comprend 18Expand