• Publications
  • Influence
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control
  • M. Choi, Sung-No Lee, +4 authors H. Lee
  • Physics, Computer Science
  • IEEE Custom Integrated Circuits Conference
  • 17 November 2008
TLDR
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. Expand
  • 26
  • 1
A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure
TLDR
A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. Expand
  • 7
  • 1
Continuous-time ΔΣ modulator having time-interleaved switched-capacitor brief-return-to-zero DAC with first-order jitter noise shaping
A continuous-time delta-sigma modulator (CT DSM) having a time-interleaved switched-capacitor brief-return-to-zero DAC with first-order jitter noise shaping is proposed to reduce the sensitivity toExpand
Double-sampled ΔΣ modulator with 1.5-bit FIR feedback DAC for reduced noise folding and increased power efficiency
A double-sampled delta-sigma modulator (DSM) with a 1.5-bit finite impulse response (FIR) feedback digital-to-analogue converter (DAC) is proposed to avoid noise folding due to the mismatch betweenExpand
Multi-Channel Audio CODEC with Channel Interference Suppression
TLDR
A multi-channel audio CODEC with interchannel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced when all the channels are running independently. Expand