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Mixed Full Adder topologies for high-performance low-power arithmetic circuits
This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted byExpand
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Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read
This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on aExpand
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Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access
This paper investigates the impact of voltage scaling on energy and performance of STT-MRAM arrays under write access, which is well known to be energy critical. Simple analytical models of energyExpand
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Power analysis attacks to cryptographic circuits: a comparative analysis of DPA and CPA
In this paper, techniques to perform power analysis attacks to snatch confidential data from cryptographic circuits are quantitatively compared. In particular, the popular Differential Power AnalysisExpand
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Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic
In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gateExpand
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Editorial in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new yearExpand
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Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers
  • M. Alioto, G. Palumbo
  • Computer Science
  • IEEE Transactions on Circuits and Systems II…
  • 18 June 2007
In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried outExpand
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The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits
In this paper, the discretized Tent map is analyzed as a source of pseudorandom bits. To evaluate the performance of the proposed pseudorandom bit generators (PRBGs), different issues wereExpand
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High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD
This work demonstrates the successful integration of 0.85nm-EOT Si<inf>0.45</inf>Ge<inf>0.55</inf>-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up toExpand
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Uniform-Distributed Noise Generator Based on a Chaotic Circuit
In this paper, the guidelines to design a true random number generator (TRNG) circuit of uniform distributed numbers. The approach is proposed for a TRNG based on a one-dimensional piecewise-linearExpand
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