• Publications
  • Influence
Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors
This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is usedExpand
  • 82
  • 4
Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors
The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data.Expand
  • 30
  • 4
Effective channel length in Junctionless Nanowire Transistors
The aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors.Expand
  • 7
  • 3
Threshold voltage in junctionless nanowire transistors
This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional PoissonExpand
  • 85
  • 2
Analog performance and application of graded-channel fully depleted SOI MOSFETs
The performances of the single-transistor operational transconductance amplifiers (OTAs) implemented using graded-channel (GC) and a conventional fully depleted silicon-on-insulator nMOSFETs areExpand
  • 71
  • 2
Charge-based compact analytical model for triple-gate junctionless nanowire transistors
Abstract A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin heightExpand
  • 19
  • 2
  • PDF
Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects
An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device isExpand
  • 66
  • 1
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
Abstract A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018Expand
  • 38
  • 1
Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation
Abstract This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices withExpand
  • 33
  • 1
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistorsExpand
  • 14
  • 1