We present two novel designs for fixed-point decimal multiplication that utilize decimal carry-save addition in the iterative portion of the design is presented.Expand

17th IEEE Symposium on Computer Arithmetic (ARITH…

27 June 2005

TLDR

This paper presents a novel design for fixed-point decimal multiplication that utilizes a simple recoding scheme to produce signed-magnitude representations of the operands thereby greatly simplifying the process of generating partial products for each multiplier digit.Expand

This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry- save addition and one that employs binary carry-save addition.Expand

18th IEEE Symposium on Computer Arithmetic (ARITH…

25 June 2007

TLDR

This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 standard for floating point arithmetic (IEEE 754R).Expand

This paper presents a fully parallel decimal floating-point multiplier compliant with the recent draft of the IEEE P754 Standard for Floating-point Arithmetic (IEEE P754).Expand

We investigate the motivation for decimal computer arithmetic, a brief history of this arithmetic, and relevant software and processor support for a variety of decimal arithmetic functions.Expand

This paper addresses the potential speedup achieved by using decimal floating-point hardware, instead of software routines, on a high-performance superscalar architecture.Expand