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Decimal multiplication via carry-save addition
TLDR
We present two novel designs for fixed-point decimal multiplication that utilize decimal carry-save addition in the iterative portion of the design is presented. Expand
Decimal multiplication with efficient partial product generation
TLDR
This paper presents a novel design for fixed-point decimal multiplication that utilizes a simple recoding scheme to produce signed-magnitude representations of the operands thereby greatly simplifying the process of generating partial products for each multiplier digit. Expand
Decimal Floating-Point Multiplication
TLDR
This paper presents the design of two decimal floating-point multipliers: one whose partial product accumulation strategy employs decimal carry- save addition and one that employs binary carry-save addition. Expand
A high-frequency decimal multiplier
TLDR
This paper presents an iterative decimal multiplier, which operates at high clock frequencies and scales well to large operand sizes. Expand
Decimal Floating-Point Multiplication Via Carry-Save Addition
TLDR
This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 standard for floating point arithmetic (IEEE 754R). Expand
A parallel IEEE P754 decimal floating-point multiplier
TLDR
This paper presents a fully parallel decimal floating-point multiplier compliant with the recent draft of the IEEE P754 Standard for Floating-point Arithmetic (IEEE P754). Expand
Improved combined binary/decimal fixed-point multipliers
TLDR
This paper presents several combined binary/decimal fixed-point multipliers that use the BCD-4221 recoding for the decimal digits. Expand
Algorithms and hardware designs for decimal multiplication
TLDR
We investigate the motivation for decimal computer arithmetic, a brief history of this arithmetic, and relevant software and processor support for a variety of decimal arithmetic functions. Expand
Potential speedup using decimal floating-point hardware
TLDR
This paper addresses the potential speedup achieved by using decimal floating-point hardware, instead of software routines, on a high-performance superscalar architecture. Expand
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