M. Wegrzyn

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Embedded processor cores, which are widely used in SRAM-based FPGA applications, are candidates for SEU (Single Event Upset)-induced faults and need to be tested occasionally during system exploitation. Verifying a processor core is a difficult task, due to its complexity and the lack of user knowledge about the core-implementation details. In user(More)
Molecular electronics based on structures ordered as neural networks emerges as the next evolutionary milestone in the construction of nanodevices with unprecedented applications. However, the straightforward formation of geometrically defined and interconnected nanostructures is crucial for the production of electronic circuitry nanoequivalents. Here we(More)
The fast control unit of telecommunication system is represented as Mealy finite-state-machine. The method of hardware optimization in the logic circuit of such control unit is proposed. Method is based on matching of different codes to the equal microinstructions in the different subtables of direct structural table of Mealy finite-state-machine. An(More)
A new method of Moore FSM circuit optimization is proposed, which is based on generation of both codes of the states and codes of the classes of pseudoequivalent states of FSM. The presented method permits to encode the states of FSM in such manner that some microoperations can be implemented using single LUT element. Other microoperations should be(More)
Reaction of [PtCl(2)(dmso)(2)] with 2,5-(dialkoxyphenyl)pyridine in HOAc leads to a dinuclear, acetate-bridged, metal-metal bonded complex of platinum(III); dmso in the presence of acid is found to be responsible for the oxidation. The dimer is analogous structurally to Pd(III) dimers implicated in catalytic acetoxylation. Platinum dimers with longer alkoxy(More)
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