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A complete 65nm CMOS platform, called LP/GP mix, has been developed employing thick oxide transistor (1.0), low power (LP) and general purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+mask only) and saves over 35% of dynamic power with the use of the low(More)
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature I/sub on/= 820/spl mu/A//spl mu/m/340 /spl mu/A//spl mu/m at I/sub off/ =(More)
This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to an important biaxial tensile stress generated by Ge predoping. Very simple and epitaxy-free, this architecture(More)
In this work, we present an investigation of the gate reoxidation step on the short channel effect. The thicker the thermal oxide, the stronger the roll-down of the threshold voltage on the NMOS transistor. This major result lead us to develop an alternative process for nitride spacer with the pad deposited TEOS that behaves as a convenient etch stop layer(More)
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