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Journals and Conferences
We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the… (More)
A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.
We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm<sup>2</sup>/Vs @ 1MV/cm) at the thinnest T<sub>inv</sub> (1.4 nm) reported to date. These stacks are formed by capping HfO<sub>2</sub> with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements… (More)
The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to… (More)
Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.
The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold… (More)
The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as… (More)
Gate-First Processing M. Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, C. Dewan, D. Park, H. Bu, W. Natzle, W. Yan, C. Ouyang, K. Henson, D. Boyd, S. Callegari, R. Carter, D. Casarotto, M. Gribelyuk, M. Hargrove, W. He, Y. Kim, B. Linder, N. Moumen, V.K. Paruchuri, J. Stathis, M. Steen, A. Vayshenker, X. Wang, S. Zafar, T. Ando, R. Iijima, M.… (More)
A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate… (More)
A new concept in high performance VLSI called Simplified Hybrid Orientation Technology (SHOT) is introduced. This novel process flow creates circuits with independently oriented surface channels for pMOS and nMOS by integrating FinFETs with planar Ultra-Thin SOI (UTSOI) MOSFETs for the first time. The unique CMOS structure enables high mobility surface… (More)