M. Schaekers

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This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with(More)
In this paper, the authors report the impact of polycrystalline Si structure on the NMOS transistor performance with a HfSiON/Ni-FUSI (fully silicided) gate. For polycrystalline films, as deposited grain structure was predominantly columnar at heater temperatures 690-730degC, except in the presence of hydrogen where the grains assume a random(More)
This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For(More)
SiON gate dielectric is optimized for general purpose 65 nm node applications by using a first nitridation approach. A process parameter screening is done where the resulting SiON films are analyzed by angle resolved XPS and non-contact probing by Quantox. Good correlation between XPS and Quantox results are found. We demonstrate also correlation between(More)
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