M. Sadollahy

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
This paper describes the high-speed and highly-linear CMOS sample/hold circuit that was used in front end of an ADC. The architecture of sample/hold based on an open-loop structure that enables it operates in high speed. The sample/hold consists of highly linear open-loop buffer and bootstrapped switch. Spice simulation with 0.35-um CMOS BSIM3v3 model(More)
  • 1