M. Riedmüller

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Notice: This document has been provided by the contributing authors as a means to ensure timely dissemination of scholarity and technical work on a noncommercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that(More)
A reconfigurable data-driven arithmetic datapath architecture for ALUs is presented which may be used for custom computing machines, Xputers and other adaptable computer systems as well as for rapid prototyping of high speed datapaths. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units(More)
An FPGA architecture (reconfigurable datapath architecture, rDPA) for word-oriented datapaths is presented, which has been developed to support a variety of Xputer architectures. In contrast to von Neumann machines an Xputer architecture strongly supports the concept of the “soft ALU” (rALU). Fine grained parallelism is achieved by using simple(More)
A scalable, parallel, and reconfigurable datapath architecture (rDPA) is presented. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The rDPA is scalable to arbitrarily large arrays and reconfigurable to be adaptable to the computational problem. Pipelining is supported by the(More)
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