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The topology of an Electrical Distribution System (EDS) can be suitably modified to minimize the real losses. Basically, losses in an EDS arise due to two factors: 1) fault in the network 2) overload in the feeders. The power losses occurring due to overload or uneven load are dealt in this paper. EDS is normally unevenly loaded and hence often need load(More)
Energy consumption has become one of the important factors in digital systems. Storage elements and the clock distribution of an IC consumes large power in case of Synchronous design. Energy efficiency which plays the critical role in low power circuit design is improved by using double edge-triggered flip-flops (DETFFs), since they can maintain the same(More)
In VLSI (Very Large Scale Integration) design the power consumption is increased for more transition memory elements. Flip-flop (FF) are the basic sequential components used for memory applications. An adder and multiplier are designed using Multi-Bit Flip-Flop (MBFF). In the proposed work one of the promising ways to improve performance of FF is merging of(More)
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