M. Nagarajan

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A 12-Gb/s transceiver in 32-nm bulk CMOS in described. Features include an 8.8–12.4-GHz LC-PLL with 0.4-ps jitter; a full-swing DLL and phase interpolator with LSB=2.6 ps and DNL≪1.2 ps; a 4.2-mW receiver front end with de-muxing comparator and precharge removal latch; and an all-digital duty cycle correction (DCC) loop. The transceiver(More)
This microprocessor is optimized for the desktop. The chip contains architectural, circuit, and technology enhancements that include a 32 kB, 2-way set associative virtual instruction cache, a 16 kB, dual-read-ported, physical data cache, and advanced branch prediction. Circuit enhancements include a 6.0 ns integer multiplier, a 19.5 ns floating-point(More)
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