M. Mohamed Asan Basiri

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This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance computation with greater accuracy. In general, digital signals are represented as a sequence of signed/unsigned(More)
Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives(More)
This paper proposes a novel fixed point complex number multiply accumulate circuit, which is used in real time digital signal processing applications. The proposed architecture consists of multiplier-cum-accumulator which can be used as multiplier as well as MAC. Here the previous MAC result is added as one of the partial products of the current(More)
This paper proposes an effective algorithm to design a larger multiplexer using a tree of smaller multiplexers for a particular user defined library. The proposed algorithm outputs the larger multiplexer into a tree based structure, which gives the scope to pipeline the larger multiplexer as per the requirements of data path design. The experimental result(More)
This paper proposes a novel fixed point multiplier architecture with data level parallelism. That is, the same multiplier hardware is used to perform multiple multiplications on different data paths. Here, we proposed a Wallace tree multiplier to perform more number of multiplications in parallel with fewer extra carry save stages than conventional(More)
This paper proposes an efficient VLSI architecture for discrete Hadamard transform, which is used in real time digital signal processing applications like image coding, MPEG, and CDMA etc. The proposed N-point Hadamard transform architecture consists of signed carry save adder tree. So the depth of the architecture falls within the bounds of O (log2 N). The(More)
A high speed and reduced-area 2-D discrete wavelet transform (2-D DWT) architecture is proposed and the design is simulated. Initially modifications are made to the lifting scheme, and the intermediate results are recombined and stored to reduce the number of pipelining stages. The architecture uses three basic 1D-DWT image processing elements. The proposed(More)