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This paper describes a previously unreported phenomenon wherein NMOS transistors of identical gate length exhibit a significant sensitivity to layout. Drive current may be reduced up to 13%, depending on diffusion overlap of gate. Mobility reduction, induced by stress from the trench isolation edge, is the root cause of the performance degradation. PMOS(More)
Shallow Trench Isolation (STI) has been the isolation scheme of choice for sub0.25μm technologies. One of the challenges of scaling STI to 0.13μm and beyond is the control of Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly impacted by the stress due to trench processing. We also show that Vt and leakage of(More)
We report on an anomalous off-state leakage current found in NMOS devices fabricated with a pre-amorphizing (PA) implant before titanium silicide formation. We present data which indicates that the leakage current is caused by channeling of the arsenic PA implant through the polysilicon gate. An angled PA implant is shown to prevent the channeling and allow(More)
The effect of floating polysilicon doping on electron injection barrier height and therefore the PROGRAM/ERASE window of an electrically erasable programmable ROM (EEPROM) cell has been studied. The introduction of dopant and the concentration of electrically active sites at the floating-gate polysilicon/tunnel oxide interface influence the electron(More)
A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions(More)
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