M. Karthigai Pandian

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This paper deals with the study of modelling double gate silicon nanowire transistors. The scaling of nanowire transistors to 10nm and below is discussed for acceptable short-channel effects and the quantum mechanical effects caused by ultrathin silicon devices considered in modelling the threshold voltage is studied. Similarly, the variation of threshold(More)
In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are(More)
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