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In common agreement with Negative Bias Temperature instability (NBTI) as a serious Front-end reliability issue, great efforts were made in recent years to investigate NBTI mechanism, characterization techniques and performance improvement. In this work authors focused on device NBTI performance improvement from combined impact of multiple process steps(More)
Abstruct Behavior of basic and complex logic gates using complementary pass-transistor logic (CPL) under various single-stuck faults are investigated. The result shows that all stuck-on faults in the basic CPL gates can be detected by current monitoring, but no logic monitoring is possible. Similarly all bridging faults between gate and source of basic CPL(More)
With advancement in technology node of silicon CMOS FEOL (Front-end-of-line) process, gate oxide quality is vital to address gate oxide reliability issues. Introduction of O<inf>2</inf> gas Ash process to remove photo resist after poly etch and polymer after spacer etch process was found to be very distinctive and advantageous to improve reliability as well(More)
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