M. Jayasanthi

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
Clock distribution networks synchronize the flow of data signals among synchronous data paths. The Performance of VLSI circuit is limited by clock distribution network since it consumes more power. This paper reviews a number of clock distribution network and presents analysis of their effectiveness and limitations, especially on energy efficiency. In this(More)
In this paper, a novel approach to develop parallel-pipelined architectures for the Fast Fourier transform (FFT) is introduced. The folding transformation and register minimization techniques are proposed for modeling FFT architectures. Novel parallel-pipelined 8-point radix-2 FFT architecture for the computation of complex valued Fast Fourier transform is(More)
The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can be integrated with recent, commercial DFT techniques, LP-TPG for in-field testing and in-field diagnostic data collection. To find maximum faults, structural diagnosis is used which does reveal the diagnostic information. A new low power test pattern(More)
  • 1