Learn More
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO<sub>2</sub> based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T<sub>inv</sub> values of &#x002DC;5 &#x000C5; and &#x002DC;8 &#x000C5; respectively for both n and pMOS devices. The drive currents at I<sub>off</sub>=100(More)
Two soybean cDNA clones, SPK-3 and SPK-4, encoding putative protein kinases were isolated and characterized. Both cDNAs encoded approximately 40-kDa serine/threonine kinases with unusual stretches of acidic amino acids in their carboxy-terminal regions, which are highly homologous to PKABA1 from wheat and ASKs from Arabidopsis. These kinases are encoded by(More)
We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform(More)
This paper demonstrates for the first time a low cost, low complexity process CMOS Hk/MG for low-power applications with Vth controlled by gate Ion-Implantation (I/I) and High-k capping for NMOS and PMOS, respectively. Novel advanced electrical and physical characterizations provide unique insights about the underlying mechanism of Vth adjust induced by I/I(More)
We report on gate-last technology for improved effective work function tuning with &#x223C;200meV higher p-EWF at 7&#x00C5; EOT, &#x223C;2x higher f<inf>max</inf> performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1)(More)
We report on aggressively scaled RMG-HKL devices, with tight low-V<sub>T</sub> distributions [&#x03C3;(V<sub>Tsat</sub>) ~ 29mV (PMOS), ~ 49mV (NMOS) at L<sub>gate</sub>~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and(More)
This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs.(More)
The impact on the reliability of capping layers for low V<inf>t</inf> nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is(More)
This paper overviews integration challenges of low-V<inf>T</inf> gate-first CMOS featuring one metal gate electrode and one host dielectric with Al<inf>2</inf>O<inf>3</inf> and La<inf>2</inf>O<inf>3</inf> cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V<inf>T</inf> enabling technologies are compared(More)