M. Hofmeister

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Hardware desrgn u7)der the use of the hardware de-scrtptiol) language VHDL has to consider three tnde-penden t property scales that /7/.J/aen ce the de.wyn process from an abstract l~vel 10 (j(ti~ leuel, namely the destgn W(w. the tm)tng aspect, aIId the value represen-taiton. The well known Y-char{ ntodel is not sutiable to descrilw these property scales(More)
This deliverable D4.2 describes the sensing techniques that are used to identify primary users (PMSE and DVB-T) in the TV White Spaces as required for the first regulatory scenario in COGEU reference architecture. The analysis of the simulation results leads to the selection of a specific spectrum sensing technique for integration with the COGEU TVWS(More)
In the area of hardware design, automata are often real-cred synchronously by a clocked state register, a next state logtc block representing the state transition function, and an output logic block representing the output functzon, As-surmng that combinatorial blocks of automata are already optzmized, a further potential for timing optimization occurs , if(More)
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