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This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Analog circuit Synthesis), in which an approach for selection of alternatives based on the evaluation of mutation values is developed, and design automafion for high performance comparators is covered.
An iterative simulation environment for reliability problems due to long-term circuit degradation has been developed for use in SPICE-like simulators. A model developed for the NBTI (negative bias temperature instability) degradation effect in the standard Verilog-A language can be used with this reliability simulator. Integration in a design environment… (More)
This article describes the development and realization of a synthesis p v g r a m for CMOS comparators. It was constructed following the SEAS framework for ana-log circuit design automation. Using this program, a number of comparators were synthesised, and tested using SPICE simulations. All comparators generated performed well above their design… (More)
This paper presents an analog circuit design assistance tool called Adapt. The tool can perform automatic circuit sizing over a wide range of heterogeneous design parameters. We present Adapt's architecture and the design flow, discuss important user-interface aspects of the tool, disclose details on the optimization algorithms incorporated in the tool, and… (More)