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Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the(More)
The three knobs of optical lithography, namely process factor k1, wavelength (λ) and numerical aperture (NA) have been constantly pushed to print smaller features. To get an equivalent k1 value below the fundamental limit of 0.25, double patterning (DP) has recently emerged as a viable solution for the 32nm lithography node. Various DP techniques exist such(More)
Current advanced lithography processes are based on a Critical Dimension (CD) budget of 10nm or less with errors caused by exposure tool, wafer substrate, wafer process, and reticle. As such, allowable CD variation across wafer becomes an important parameter to understand, control and minimize. Three sources of errors have an effect on CD Uniformity (CDU)(More)
  • Tae-Seung Eom, Jun-Taek Park, +9 authors M. Dusa
  • 2008
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask are used for this(More)
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