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The hot electron induced mechanism disturbing the stored information in inhibited bit lines during the programming of nonvolatile memories with NAND architecture is studied in detail using a new dedicated advanced physical simulation scheme for the first time.
Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold… (More)
Capacitors with a dielectric material consisting of amorphous laminates of Al2O3 and TiO2 with subnanometer individual layer thicknesses can show strongly enhanced capacitance densities compared to the bulk or laminates with nanometer layer thickness. In this study, the structural and dielectric properties of such subnanometer laminates grown on silicon by… (More)
On TANOS (Tantalum Alumina Nitride Oxide Silicon) charge trap cells an anomalous effect is observed during cell erase operation. Different TANOS cell architectures are investigated including an encapsulation liner of different thickness. Especially on cells fabricated without such a liner an unintended programming is observed and characterized in detail. A… (More)
This work reports the feasibility of silicon and silicon germanium epitaxy using an ASM A412(TMa) LPCVD all quartz, hot wall, vertical batch furnace reactor using 100 wafer product loads. The very same furnace can be used for 25 wafer and 200 wafer load size, without any hardware changes, dependant on production needs. Following this approach a significant… (More)