M. Brocard

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In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell(More)
Stacking N over CMOS devices using 3D Sequential CoolCube&#x2122; Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 10<sup>8</sup>/mm<sup>2</sup> achievable. In addition, we presented(More)
In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted - silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The(More)
In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the(More)
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