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Transactional Memory(TM) is a promising way to coordinate concurrent threads in multi-core processors. Software transactional memory (STM) can run on conventional processors without additional hardware support. It is an option before TMs are available in commercial multi-core processors. Several TM systems use signatures to track items read and written(More)
Transactional Memory(TM) is a promising way to coordinate concurrent threads in multi-core processors. Software transactional memory (STM) can run on conventional processors without additional hardware support. In this paper we propose VectorSTM which reduces the cost of centralized concurrency control. VectorSTM employs distributed vector timestamps(More)
With the progress of semiconductor manufacture techniques and the development of processor architecture, the gap between processor and DRAM speed is becoming larger and larger, memory bandwidth is now the primary bottleneck of improving computer system performance. Modern DRAM provide several independent memory banks, according to this character, we present(More)
Recently-proposed processor micro-architectures for high Memory Level Parallelism (MLP) harvest substantial performance gains. Unfortunately, Miss-Handling architectures (MHAs) of current cache hierarchies are too limited to support the requirement of high MLP system. This paper proves the number relation of MHA entries between L1 and L2 cache, presents an(More)
As the gap between processor and memory performance increases, performance loss due to long-latency memory accesses become a primary problem. Memory-level parallelism (MLP) improves performance by accessing memory concurrently. An effective system performance analysis model and method is lacked for these researches. Using queuing theory, we establish a(More)
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