Luis E. Toledo

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This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity­ to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm(More)
a new CMOS voltage reference, which takes advantage of the temperature dependence of NMOS and PMOS threshold voltages, is presented. Due to the circuit architecture the mobility factor is completely cancelled. It does not use resistors and all transistors works in strong inversion. The circuit is simple, opamp-less and can be implemented in a standard CMOS(More)
The design and test of a mixed-signal 9.6Kb/s FSK transmitter-receiver is presented. It is aimed for digital communications through the domiciliary power lines as needed by a networked electrical power management and measuring system wherein the circuit must be embedded. For the desired baud rate the bit carriers frequencies of 111KHz (logical 0) and 125KHz(More)
A new low-voltage electrically tunable transconductor is presented. Its transconductance can be settled by means of a ratio between a reference current and a reference voltage rendering the circuit independent of technological parameters, to a first order approach. This property allows, to some extent, reusing the transconductor in several CMOS processes. A(More)
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