This paper considers the problem of designing heterogeneous multiprocessor embedded systems. The focus is on a step of the design flow: the definition of innovative metrics for the analysis of the system specification to statically identify the most suitable processing elements class for each system functionality. Experimental results are also included, to… (More)
This paper introduces an enhanced hardware/software co-design framework allowing the designer to introduce hardware fault detection properties in the system under consideration. By considering reliability requirements at system level, within a hw/sw co-design flow, it is possible to evaluate overheads and benefits of different solutions. System… (More)
—Secure monitoring services supported by flexible, manageable, and cheap systems in areas where ordinary networks are unsuitable: this is one of today challenges in health monitoring engineering. Wireless Sensor Networks represent a promising technological solution but resource constraints and exposure to external attacks could limit their employment. The… (More)
In this paper a comprehensive methodology for software power estimation is presented. The methodology is supported by rigorous mathematical models of power consumption at three different levels of abstraction. The methodology has been validated in a complete framework developed within the TOSCA co-design environment.
This paper addresses the problem of designing heterogeneous multiprocessor embedded systems. The paper focuses on the basic steps of a proposed design flow with particular emphasis on the partitioning activity and the related metrics composing the cost function used to evaluate candidate design alternatives. Experimental results are also included, to show… (More)
The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level,… (More)
—Continuous advances in silicon technology enable the development of complex System-on-Chip as cooperation among Digital Signal Processors (DPSs), General Purpose Processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus… (More)