Lucio Rodoni

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A 60 GHz cross-coupled differential LC CMOS VCO is presented in this paper, which is optimized for a large frequency tuning range using conventional MOSFET varactors. The MMIC is fabricated on digital 90 nm SOI technology and requires a circuit area of less than 0.1 mm 2 including the 50 Ω output buffers. Within a frequency control range from 52.3 GHz to(More)
—In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS(More)
—A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation(More)
Source-series-terminated (SST) drivers offer the advantage of providing a large range of termination voltages, making them particularly suitable for multi-standard I/Os [1, 2]. Many standards (e.g. [3]) however, call for larger vertical eye openings that require raising the dc supply voltage from the l.OV limit for thin-oxide devices in 65nm technology to(More)
Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supply have been achieved for CMOS inverters fabricated on a 90 nm silicon on insulator technology. The results are measured with an optimised CMOS ring oscillator. These are believed to be the lowest gate delays reported to date for CMOS inverters at room temperature. Introduction: The increase(More)
—A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10-12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a small(More)
In this paper, an integrated 2-to-1 selector multiplexer in 90-nm complementary metal-oxide semiconductor (CMOS) digital technology is presented. The multiplexer is based on a differential Gilbert-cell structure. Peaking inductors are used to improve the bandwidth. At a supply voltage of 1.2 V, a speed performance of 24 Gbls is achieved. The circuit core(More)
An ultra low power consuming low noise amplifier (LNA) at C-band with variable gain for adaptive antenna combining is presented in this paper. The microwave monolithic integrated circuit (MMIC) was fabricated using commercial 0.25 µm bipolar complementary metal oxide semiconductor (BiCMOS) technology. At 5.2 GHz, a supply voltage of 1.2 V and a current(More)
This paper investigates the influence of parasitic interconnections on high speed logic gates. A complementary metal oxide semiconductor logic (CMOS) gate, a high speed source coupled logic (SCL) gate and a low power SCL gate are compared. The important impact of the wiring parasitics on the speed performances is pointed out. The results are confirmed with(More)
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