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Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic(More)
The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. This paper presents a global toolset architecture for testability analysis and test pattern generation.(More)
Veri cation of the functional correctness of VHDL speci cations is one of the primary and most time consuming task of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the speci cation by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic(More)
The paper selected as the most outstanding in the field of CAD is: Symbolic Functional Vector Generation for VHDL Specifications by Fabrizio Ferrandi, Luca Gerli, and Donatella Sciuto of Politecnico di Milano, Italy and Franco Fummi of Università di Verona, Italy. The authors present a methodology for functional verification of VHDL specifications based on(More)
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