Luca Gerli

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Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic(More)
Veriication of the functional correctness of VHDL spec-iications is one of the primary and most time consuming task of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the speciication by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based o n symbolic(More)
The presented methodology is under development in the OMI/ESPRIT 20616 Project – REQUEST (REuse and QUality ESTimation). Abstract The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in(More)
Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the most outstanding papers of previous year's conference. The selection is based on the results of the reviewing process and the voting by the conference participants. The authors present a methodology for functional verification of VHDL specifications based on(More)
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