Luca Gerli

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Veriication of the functional correctness of VHDL spec-iications is one of the primary and most time consuming task of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the speciication by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based o n symbolic(More)
The presented methodology is under development in the OMI/ESPRIT 20616 Project – REQUEST (REuse and QUality ESTimation). Abstract The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in(More)
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