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A hardware emulator based approach has been developed to perform test evaluation on large sequential circuits (at least tens of thousands of gates). This approach relies both on the flexibility and on the reconfigurability of hardware emulators based on dedicated reprogrammable circuits. A Serial Fault Emulation (SFE) method in which each faulty circuit is(More)
Design productivity of MPSOC is a major challenge for semiconductor industry. Low design productivity affects concurrent engineering on increasingly software dominated SOC design. In this paper we describe automatic design methodologies for MPSOC and prototyping on multi-FPGA platforms which allows fast design productivity. Case studies of actual(More)
  • Cedric Alquier, Stephane Guerinneau, Lauro Rizzatti, Luc Burgun
  • 2003
In this paper, we examine a co-simulation solution between SystemC and a new generation emulator called ZeBu. SystemC is a C++ hardware description library that supports design modeling from the RT level to the system level. SystemC is part icularly effective for IP and embedded systems verification. ZeBu is a hardware verification product built on a PCI(More)
The traditional approaches for multilevel logic optimization involve representing Boolean functions in Sum-of-Product forms that are minimized and then factorized in multilevel expressions. We have investigated an alternative approach called graphic synthesis that is based on a set of Reduced and Ordered BDDs, namely a multi-ROBDD for representing Boolean(More)
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